A Cryogenic Hybrid Photonic/CMOS Controller Architecture for Scalable Superconducting Qubit Control

Abstract

Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.