arXiv · 2609.12389
Error-Rate Reduction in LDPC Decoding via Bit-Aligned Temporal Reinforcement in Parallel Probabilistic-Bit Dynamics
Abstract
Probabilistic bits (p-bits) provide a physical and algorithmic primitive for stochastic inference, but highly parallel updates can alter their collective dynamics. We study the decoding of random-regular (3, 6) low-density parity-check (LDPC) codes using Jacobi-type p-bit annealing with stochastic partial activation. An additive response-path rule stores each bit's saturated response and reuses it before stochastic readout. High-statistics simulations with independent parameter optimization for each method show pooled bit-error-rate reductions of 33.5%, 74.8%, and 81.8% relative to memoryless probabilistic simulated annealing (pSA) for representative codes of block lengths 96, 192, and 288, respectively. Static gain, normalized averaging, response shuffling, and same-bit binary-state feedback with only its coefficient tuned under the same nonmemory parameters do not reproduce the full saturated-response benefit. Trajectory analysis links the improvement to acquisition of the channel-consistent valid-codeword basin and enhanced post-acquisition stability; the acquisition advantage persists from random and channel-hard-decision starts under the tested conditions. Across all 30 independent code realizations, fixed additive parameter-and-readout packages achieve lower bit- and frame-error rates than separately optimized pSA-specific packages, with neither package retuned for individual codes. These results show that the computational effect of temporal state depends on the retained quantity and its reinjection into stochastic dynamics.
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Naoya Onizawa, Takahiro Hanyu. 2026-09-11. Error-Rate Reduction in LDPC Decoding via Bit-Aligned Temporal Reinforcement in Parallel Probabilistic-Bit Dynamics. https://arxiv.org/abs/2609.12389
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