Rect3D: A Unified Analytical Framework for 3D-IC Rectilinear Floorplanning

Abstract

3D-ICs offer significant performance improvements for modern VLSI designs by reducing global interconnect cost. However, conventional 3D floorplanning methods decompose the problem into separate inter-die partitioning and intra-die floorplanning stages, which can restrict the design optimization space and limit the potential gains. Although directly modeling and optimizing in 3D space can mitigate this limitation, the high computational complexity hinders algorithmic efficiency. To address these challenges, we propose \textsc{Rect3D}, an analytical 3D rectilinear floorplanning framework that integrates probabilistic inter-die block assignment into a unified continuous optimization model. The framework combines graph Laplacian initialization for topology-aware seeding, a scalable gradient-based global optimization procedure for joint die assignment and geometric refinement, and a 3D grid-based legalization method for generating connected rectilinear layouts. On GSRC benchmarks, \textsc{Rect3D} reduces wirelength by up to 83.6\% and runtime by up to 15.98$\times$ compared with representative state-of-the-art 3D floorplanning baselines. It also consistently achieves the lowest wirelength among six additional partition-first rectilinear baselines, showing the advantage of preserving die assignment and in-die geometry in a unified 3D optimization flow.