Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network

Ashish Sharma; Alia Long; Keith D. Mecham; Ioannis Savidis

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arXiv · 2609.33281

Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network

Ashish Sharma·Alia Long·Keith D. Mecham·Ioannis Savidis

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Abstract

Electromagnetic side channels have been extensively utilized in non-invasive attacks or analyses to extract critical information from deployed systems. Most of the attacks or analyses are typically executed on cryptographic algorithms under the assumption that the underlying implementation remains fixed. The assumption is valid in the context of fixed hardware, where modifications to the circuit are not made after manufacturing. However, in the case of adaptive hardware, including field-programmable gate arrays (FPGAs), the assumption no longer holds as modifications to the configuration of the array are permitted post-manufacturing. Consequently, this study introduces a methodology for the analysis of electromagnetic side channels of an FPGA through the study of deterministic finite state machines (DFSMs), where the effects of placement, routing, and operating frequency on the EM emanations of the FPGA due to the utilized clocking resources are characterized. To analyze the impact of frequency, device placement, and resource allocation on the EM emanations from the FPGA, statistical analysis including mean difference and variance difference calculations of measured EM fields were utilized to identify points of high EM activity on a set grid of sampled points. A 1.32x increase in flagged grid points was observed in the analysis of the mean difference when the percentage of utilized clock resources was increased from 25% to 90%. Similarly, a 1.39x increase in flagged grid points was observed when the variance difference was calculated for the same increase in clock resources.

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Ashish Sharma, Alia Long, Keith D. Mecham, Ioannis Savidis. 2026-09-27. Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network. https://arxiv.org/abs/2609.33281

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