Co-design of Silicon Microring Modulator beyond 200 Gb/s per Lane: Device Physics, Operating Point, and Compact Models for Scale-Up and Scale-Out Optical I/O

Abstract

Optical input/output (I/O) supports high-bandwidth communication between processors in artificial intelligence (AI) systems. Depletion-mode silicon microring modulators offer compact footprints, wavelength multiplexing and femtojoule-scale junction switching energy per bit. However, as lane rates increase to 200~Gb/s and beyond, a digital signal processor (DSP) performing equalization and forward-error correction can consume up to half of the optical module power. We analyze the junction and cavity physics of silicon microring modulators, relating modulation efficiency, capacitance, optical loss and coupling to bandwidth and drive requirements to guide device optimization above 200~Gb/s per lane. Laser detuning and optimal operating points are examined by distinguishing maximum static slope, static and dynamic OMA, and gain--bandwidth product (GBW), including the influence of the junction RC response. The effects of optical self-heating, photocarriers and bias-network voltage droop on the resonance are discussed together with heater tuning and wavelength assignment in DWDM arrays. Cold-resonance design points are calculated from the required hot detuning, link-budget-derived optical power and assumed thermal parameters, with heater reserve and startup acquisition included as design constraints. A compact model of the coupled electrical, optical and thermal dynamics is used to evaluate PAM4 eye diagrams, and a Verilog-A implementation of the model core is provided for circuit-level simulation.