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arXiv · 2610.02936

A Timing-Robust Frequency-Interleaved ADC with Embedded Analog Fourier Transform

Xingchen Chao·Yunqiang Xu·Qiang Yu·Christian Adam·Qiang Li
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Abstract

Timing errors represent a fundamental challenge in high-speed analog-to-digital converters (ADCs). This paper presents a frequency-interleaved architecture with inherent robustness to timing errors. The frequency interleaving is achieved by an embedded analog Fourier transform (AFT), allowing accurate channel spacing. The charge-based passive AFT is able to share the capacitor array with the capacitive DAC of the subsequent data conversion. A circuit implementation for the complex-valued irrational coefficients in the AFT matrix is proposed, which eliminates the device-ratio-induced systematic errors. Measured at 10b 13GS/s, the calibration-free ADC achieves 45.8-dB SNDR and 56.1-dB SFDR at Nyquist. The ADC consumes 26.4mA from a single 1V supply, resulting in a Walden FoM of 12.7 fJ/conv.-step.

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Xingchen Chao, Yunqiang Xu, Qiang Yu, Christian Adam, Qiang Li. 2026-10-02. A Timing-Robust Frequency-Interleaved ADC with Embedded Analog Fourier Transform. https://arxiv.org/abs/2610.02936

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