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arXiv · 2610.03594

Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification

Kaavya Sahay·Cody Jones
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Abstract

For quantum low-density parity check (qLDPC) codes, the ability to manipulate individual logical units of information, i.e. the use of addressable gates, enables maximal utility of their efficient encoding. We introduce explicit low-depth unitary circuits that realize fully addressable and fault-tolerant two-qubit Clifford gates for a subset of two-dimensional translationally invariant qLDPC codes. Our transversal unitaries are created by applying a geometrically structured sparsification procedure to round-robin circuits. We verify the general applicability of our protocol by proposing and numerically simulating a range of addressable CZs between toric, cyclic hypergraph-product, color, gross, and directional codes, demonstrating fault-tolerant memory-like logical error rate scaling.

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Kaavya Sahay, Cody Jones. 2026-10-02. Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification. https://arxiv.org/abs/2610.03594

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