A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS

Abstract

The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referred offset trim is the programmed multilevel state of the ferroelectric field-effect transistor (FeFET) that converts the input. Fabricated in 28-nm CMOS, the 6.07-$μ$m$^2$ VTC consists of a current-starved inverter with the FeFET and a parallel NMOS leaker in its tail, a capacitor bank, and a following inverter. The programmed state shifts the transfer curve onto the input range, leaving the gain to the capacitor bank and the leaker bias. Measured at 10~MS/s, centered states weaken the second harmonic from $-$12.5~dB in the low-threshold state to $-$32.2~dB and lower the static integral nonlinearity (INL) at 5~bit from 2.42 to 0.92~LSB. Post-layout simulations indicate that the proposed VTC can operate at 500~MS/s, drawing 2.0~$μ$W from a 0.9-V supply, with nearly unchanged distortion and gain up to 700~MS/s. Across simulated process corners and $\pm$10\,\% supply variation, the input-referred offset is calibrated to within 10~mV and the gain to within 4\,\% of nominal by adjusting the programmed state and leaker bias.