Toward Partitioned Reference Readout for Four-Level IGZO Memory: Device Statistics, Confusion Matrices, and INT4 Error Propagation

Abstract

Four-level indium-gallium-zinc oxide (IGZO) 2T0C memory needs reliable state formation, sensing references, and a path from cell errors to digital weights. We analyze 107 measured DC transfer curves from 37 isolated IGZO transistors (W/L = 3/0.5 micrometers). Four gate-bias operating points inferred from the first sweep are evaluated on later sweeps of 35 devices. Device-resolved operating points reduce second-sweep across-device current standard deviation by 49.4-52.4%, yet retaining initial thresholds increases misclassified points from 37/140 to 55/140. Leave-one-device-out reference estimation gives 0/140 on the second sweep; freezing second-sweep thresholds yields 6/140 on the third. Sampling eight reference transistors on the third sweep gives a mean held-out error fraction of 0.15% over 2,000 selections, versus 4.33% with frozen thresholds on matched held-out devices. We present conditional confusion matrices, a counterfactual common-gain sensitivity, and an INT4 error-propagation proxy. A simultaneous four-state bank with eight reference cells per state requires at least 32 physical reference cells, 12.5% of a proposed 256-cell data bank before peripheral overhead. A charge-conservation model and a partitioned hierarchical error model specify the pulse, retention, and array measurements needed to test transfer from DC device statistics to pulsed 2T0C operation.