ZKPU: Zero-Knowledge Processing Unit for Heterogeneous Workloads

Jonathan Ku; Changchun Zhou; Jiawen Wu; Sangouk Jeon; Cong Guo; Yuzhe Fu; Bowen Duan; Dongsuk Jeon; JV Rajendran; Yiran Chen; Hai Li

arXiv · 2610.27530

ZKPU: Zero-Knowledge Processing Unit for Heterogeneous Workloads

Jonathan Ku·Changchun Zhou·Jiawen Wu·Sangouk Jeon·Cong Guo·Yuzhe Fu·Bowen Duan·Dongsuk Jeon·JV Rajendran·Yiran Chen·Hai Li

View original source ↗Read source document ↗Export metadata ↓

Abstract

Zero-knowledge proofs (ZKPs) have become a fundamental building block for privacy-preserving computation, blockchain systems, and verifiable machine learning. Modern ZKP protocols span two distinct families: curve-based protocols, which rely on large finite-field arithmetic, and hash-based protocols, which operate over native 64-bit fields. Existing hardware accelerators are specialized for one protocol family because they are built on operand-scanning Montgomery multiplication, resulting in fixed-width datapaths, poor utilization across heterogeneous operand widths, and limited scalability. This paper presents \emph{ZKPU}, a Zero-Knowledge Processing Unit for heterogeneous ZKP workloads. ZKPU introduces a new compute paradigm by co-designing finely integrated product scanning (FIPS) Montgomery multiplication with a reconfigurable Twin Systolic Fabric (TSF), enabling modular multiplication at arbitrary widths in 64-bit increments. Combined with a fine-grained Deque buffer, on-chip twiddle-factor generator, and memory-efficient MSM preprocessing strategy, ZKPU provides a unified architecture for both curve-based and hash-based protocols. Evaluation using Groth16 and Plonky2 shows that ZKPU achieves up to $144\times$ speedup for NTT, $13.6\times$ for MSM, and approximately $7.2\times$ end-to-end application speedup over state-of-the-art accelerators, while being the first architecture to efficiently support both protocol families on a single reconfigurable hardware platform.

Explore related subjects

cs.AR

Keep this discovery

Explore connections, maps & timelines

BibTeX RIS

Jonathan Ku, Changchun Zhou, Jiawen Wu, Sangouk Jeon, Cong Guo, Yuzhe Fu, Bowen Duan, Dongsuk Jeon, JV Rajendran, Yiran Chen, Hai Li. 2026-10-20. ZKPU: Zero-Knowledge Processing Unit for Heterogeneous Workloads. https://arxiv.org/abs/2610.27530

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

arXiv2026

Interflow: Breaking the Offline-Online Barrier for Private AI at the Edge

Privacy-preserving machine learning (PPML) offers a promising path toward bringing powerful AI services to the edge without exposing sensitive user data. However, its practical deployment remains constrained by the high communication, computation, and data-movement costs of secure multi-party computation (MPC), particularly during nonlinear inference. Existing MPC systems typically decouple input-independent correlated randomness generation from online execution, creating substantial memory pressure to buffer single-use cryptographic data. Moreover, limited storage can force a stop-and-refill execution pattern that repeatedly stalls the pipeline to replenish these buffers, bringing randomness generation back onto the critical path. We propose Interflow, an algorithm-hardware co-design that rethinks this separation by batch-wise processing and pipelining correlated-randomness generation with online execution: while the current batch consumes pre-generated randomness to execute secure nonlinear operations, correlation generation proceeds concurrently for the next batch. By leveraging interleaved execution, efficient data movement, and hardware acceleration, the design transforms preprocessing from a serialized, storage-intensive offline phase into a continuously overlapped pipeline that generates correlated randomness closer to the point of consumption, reducing memory footprint and data movement overhead. Implemented on the Zynq UltraScale+ ZCU102, Interflow improves nonlinear evaluation throughput by up to 1.55x for CNN operators and 1.48x for transformer operators. It achieves up to 1.26x speedup for ResNet-50 and up to 1.21x speedup for BERT-base, and reduces memory footprint by up to 37%, compared with baseline frameworks.

cs.AR↗

arXiv2026

DaPPA: A Unified Data-Parallel Programming Framework for Efficient Processing-in-Memory Execution

Processing-in-memory (PIM) alleviates data-movement bottlenecks by placing computation near or inside memory. Two general-purpose PIM paradigms are now practical: processing-near-memory (PNM) and processing-using-memory (PUM). Although both target regular, data-intensive, data-parallel workloads, they remain difficult to program because data organization is tightly coupled to computation and differs across substrates. Thus, programmers must manually manage substrate-specific data partitioning, movement, layout, and tiling, preventing program portability across PIM systems. We propose DaPPA (data-parallel processing-in-memory architecture), a programming framework that exposes a single high-level data-parallel pattern interface and retargets it to multiple PIM substrates. The key idea of DaPPA is to decouple the expression of data parallelism from substrate-specific data organization: programmers express computation once using data-parallel patterns and a dataflow interface, while specialized backends automatically generate data orchestration for PNM and multi-level tiling for PUM. We evaluate DaPPA on representative substrates from both PIM paradigms. On the UPMEM PNM system, DaPPA outperforms hand-tuned implementations by 1.6x on average with 95% fewer lines-of-code, and outperforms the state-of-the-art SimplePIM framework by 1.4x on average with 62% fewer lines-of-code. On a SIMDRAM-like PUM substrate, DaPPA outperforms the state-of-the-art MIMDRAM compiler by 2.0x on average (up to 6.4x) across 12 workloads. DaPPA can deploy all ten of our PNM workloads, whereas CINM, the closest framework targeting both paradigms, can deploy only three, on which DaPPA is 2.7--6.8x faster. We open-source DaPPA at https://github.com/CMU-SAFARI/DaPPA.

cs.AR↗

arXiv2026

GRAU: A Generic Runtime-Reconfigurable Activation-Requantization Unit for Quantized Neural Network Accelerators

As neural networks continue to scale, low-precision quantization is widely adopted in edge accelerators, but conventional multi-threshold activation hardware requires 2^n-1 thresholds for n-bit integer outputs, leading to rapidly increasing hardware costs. We propose GRAU, a Generic Runtime-Reconfigurable Activation-Requantization Unit that fuses batch normalization, nonlinear activation, and requantization through piecewise-linear fitting with Power-of-Two slopes. GRAU requires only basic comparators and 1-bit right shifters, while supporting mixed-precision quantization and runtime switching among post-accumulation functions, including modern nonlinear activations such as SiLU and GELU. Compared with multi-threshold activation-requantization units, GRAU reduces LUT consumption by approximately 90% or more while improving hardware efficiency, flexibility, and scalability. We further explore the trade-off between accuracy and hardware cost across different approximation settings and provide an open-source toolchain for GRAU-aware network training.

cs.AR↗