A Global Routing Method for Electronic Circuit Design Integrating Flow Matching and Constrained A*

Abstract

Global routing is a fundamental issue in the design of electronic circuits, as it directly relates to the efficiency, reliability, and compactness of the overall layout of integrated systems. As the demand for higher functionality and reliability within a limited chip area increases, the importance of routing as a design consideration has never been greater. Efficient global routing optimization techniques are therefore required to connect all pins with minimal wirelength (WL), while avoiding congestion and interference across multiple nets within the design space. As the number of nets to be routed increases, global routing inherently suffers from a combinatorial explosion in the design space, making it increasingly difficult to obtain feasible solutions. In this paper, we focus on solving constrained global routing problems based on a heuristic A*-based framework. Based on this concept, a hybrid approach is proposed by integrating constrained A* with flow matching (FM). The method utilizes FM to construct a global cost map that captures routing tendencies across the design space, which is then used to guide the constrained A* search process. This enables efficient exploration of the solution space while satisfying routing constraints. Experimental results demonstrate that the proposed method achieves comparable WL and via usage to baseline methods while maintaining constraint satisfaction across a wide range of scenarios. Notably, the framework shows strong capability in solving complex routing instances that are difficult to handle using conventional approaches. Additionally, the method shows robust generalization performance across different problem sizes and net configurations.