Same Function, Different CPU: Quantifying Hardware Heterogeneity in Commercial FaaS Platforms

Jonas Heisterberg; Natalie Carl; Trever Schirmer; David Bermbach

Home/Archive/arXiv

arXiv · 2611.02990

Same Function, Different CPU: Quantifying Hardware Heterogeneity in Commercial FaaS Platforms

Jonas Heisterberg·Natalie Carl·Trever Schirmer·David Bermbach

View original source ↗Read source document ↗Export metadata ↓

Abstract

Serverless computing, particularly Function-as-a-Service (FaaS), abstracts operational concerns such as scaling, scheduling, and resource management from users. This abstraction, however, conceals a heterogeneous hardware fleet on which function execution environments are scheduled behind a unified function interface. Consequently, otherwise identical invocations may run on different CPU types that differ in performance, a hardware lottery that users can neither see nor control. Since the resulting variability is entangled with other sources, such as noisy neighbors or diurnal effects, its contribution to overall performance variability and how this contribution differs across providers remain unclear. In this paper, we systematically study hardware heterogeneity and its impact on function performance across four widely used commercial FaaS platforms, covering regional, configurational, and temporal differences. Using variance decomposition, we find that CPU heterogeneity alone explains 4 % to 97 % of the performance variance on AWS Lambda and Google Cloud Run Functions. On Azure Functions, in contrast, we identify a platform-level mechanism that produces bimodal execution durations and overshadows CPU effects. We observe that the CPU composition on AWS Lambda shifts within a single week. Additionally, we reveal that on Google Cloud Run Functions and Alibaba Function Compute, the availability of instruction set extensions such as SHA-NI differs between CPU types, widening the performance gap further. Since all platforms bill by duration, performance gaps between CPU types translate directly into cost, with invocations on the slowest CPU type costing up to three times as much as those on the fastest.

Explore related subjects

cs.DC

Keep this discovery

Explore connections, maps & timelines

BibTeX RIS

Jonas Heisterberg, Natalie Carl, Trever Schirmer, David Bermbach. 2026-11-02. Same Function, Different CPU: Quantifying Hardware Heterogeneity in Commercial FaaS Platforms. https://arxiv.org/abs/2611.02990

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

arXiv2026

InfiniLoRA: Disaggregated Multi-LoRA Serving for Large Language Models

LoRA enables efficient customization of LLMs and is widely used in multi-tenant and multi-task serving. However, emerging model architectures such as MoE significantly increase LoRA memory cost, making existing coupled LoRA serving designs poorly scalable and prone to tail-latency inflation. We present InfiniLoRA, a disaggregated LoRA serving system that decouples LoRA execution from base-model inference. InfiniLoRA introduces a shared LoRA Server with parallelism-aware execution, SLO-driven provisioning, and critical-path optimizations, including GPU-initiated communication and hardware-specialized LoRA kernels. Experiments show that InfiniLoRA can achieve an average $3.05\times$ increase in serviceable request rate under strict latency SLOs, and improve the percentage of LoRA adapters satisfying the SLO requirement by 54.0\%.

cs.DC↗

arXiv2026

VeriNC: Finding Design Risks of In-Network Computing Systems

The emergence of programmable switches has brought in-network computing (INC) into the spotlight in recent years. By offloading computation directly onto the data transmission process, INC improves network utilization, reduces latency to sub-RTT levels, saves link bandwidth, and maintains throughput. However, INC disrupts the transparency of traditional networks, forcing developers to consider network exceptions like packet loss and out-of-order. If not properly handled, these exceptions can lead to violations of application properties, such as cache consistency and lock exclusion. Usual testing cannot exhaustively cover these exceptions, raising doubts about the correctness of INC systems and hindering their deployment in the industry. This paper presents VeriNC, the first general-purpose tool for verifying INC systems. VeriNC provides a high-level specification language and saves developers 67.2% lines of code on average. To help better understand the behavior of the system, VeriNC offers configurable network environments. VeriNC enables developers to express INC-specific correctness properties. VeriNC translates developer-specified systems into state transition representations, performs model checking to detect potential design risks, and reports violation traces to developers. We propose optimizations for INC-specific scenarios to address the challenge of state space explosion. We modeled INC systems across four application domains and identified design risks with VeriNC in seconds. VeriNC has also been adopted to guide the design of a new INC protocol. Based on our verification experience, we summarize lessons that help develop a correct INC protocol. We further reproduce them in real systems to confirm the validity of our verification result.

cs.DC↗

arXiv2026

Serving Chain-structured Jobs with Large Memory Footprints with Application to Large Foundation Model Serving

As a current trend in Artificial Intelligence (AI), large foundation models are increasingly employed as the core of AI services. However, even after training, serving such models at scale remains a challenging task due to their heavy resource footprints, particularly in terms of GPU memory. While recent works revealed unique characteristics of systems serving foundation models that distinguish them from traditional distributed computing systems, there is still a lack of fundamental understanding of the underlying system management problems. This work aims at addressing this gap by extracting a novel problem of "server chain composition" via block placement and cache allocation for serving chainstructured jobs with large memory footprints, which models a fundamental problem in serving large foundation models through pipeline parallelism. After showing the NP-hardness of the optimal solution, the focus is turned to developing scalable algorithms with guaranteed performance under state-of-the-art load balancing. Application of the proposed solution to a distributed large language model (LLM) serving system shows significant reduction of response times compared to state-of-the-art solutions.

cs.DC↗