A polynomial-time heuristic for Circuit-SAT

Francesco Capasso

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A polynomial-time heuristic for Circuit-SAT

Francesco Capasso

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Abstract

In this paper is presented an heuristic that, in polynomial time and space in the input dimension, determines if a circuit describes a tautology or a contradiction. If the circuit is neither a tautology nor a contradiction, then the heuristic finds an assignment to the circuit inputs such that the circuit is satisfied.

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Francesco Capasso. 2005-11-28. A polynomial-time heuristic for Circuit-SAT. https://arxiv.org/abs/cs/0511071

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