arXiv subjects

Alberto Perro

Publications and source records attributed to Alberto Perro.

3 recordsLinked to original sources

arXiv2026

A Scalable Two-Stage Back-End Architecture for 400GbE Data Acquisition Systems

A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10 Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for decoding and Ethernet conversion, followed by a Microchip META-DX2+ Ethernet PHY that aggregates these streams into a 400 GbE interface. This study evaluates the design's performance, validating it as a scalable and cost-effective architecture for next-generation HEP data acquisition systems.

physics.ins-det↗

arXiv2026

A converged architecture for processing 32 Tbps of physics data in real-time at the LHCb experiment

The LHCb detector at the Large Hadron Collider has been upgraded to acquire an unprecedented 32 Tbps of particle-collision data to provide new insights in the High Energy Physics domain. The data produced by the detector is filtered in real-time to select interesting collisions. As part of the upgrade, a pre-filtering stage has been removed leading to a factor 40 increase in data rate. To deal with the high throughput demands of LHCb real-time data processing, we present an off-the-shelf network architecture using zero-copy techniques in conjunction with an efficient, fully-GPU-based filter. Our converged architecture is able to process the full 32 Tbps of particle-collision data in real-time, the highest in any physics experiment to date. Our result extends the reach of the LHCb physics programme and sets a new standard for real-time data processing at particle physics experiments.

hep-ex↗

arXiv2025

A Low-Cost, Low-Power Media Converter Solution for Next-Generation Detector Readout Systems

High Energy Physics (HEP) data acquisition systems are often built from high-end FPGAs. As such systems scale in the HL-LHC era, severe under-utilization of FPGA transceivers can occur because front-end links prioritize radiation hardness and power consumption over raw data bandwidth. This work evaluates recently introduced low-power, low-cost FPGA devices as an alternative building block for future readout architectures. This study presents the implementation of a readout back-End on FPGA where the front-end protocol is based on the Low-Power GigaBit Transceiver (lpGBT) and the readout protocol is based on 10 Gigabit Ethernet, using the LHCb Run 4 RICH detector as a practical case study.

physics.ins-det↗