arXiv subjects

Amit Trivedi

Publications and source records attributed to Amit Trivedi.

7 recordsLinked to original sources

arXiv2026

Delta-Seeker: Closed-Loop Generative Search for Novel Circuit Design Discovery

Generative models are increasingly used for circuit synthesis and optimization by proposing topologies, sizing devices, and exploring large design spaces. We investigate whether they can instead support design discovery, where generated structures must depart from known designs while producing reproducible electrical behavior. We propose Delta-Seeker, a closed-loop circuit search framework that combines discrete diffusion for topology generation and mutation with structural checking, SPICE-in-the-loop sizing, Pareto selection, and feedback from prior search outcomes. The search controller uses progress and recurring structural failures to allocate evaluation effort and steer subsequent topology generation, while independent re-sizing and operating-corner analysis are performed only after search. In generator-only experiments, cross-generation feedback increases structurally valid children from 143 to 945 and reduces the faulty-candidate fraction from 0.925 to 0.761. In op-amp topology discovery at matched sizing cost, Delta-Seeker yields 54 designs that remain feasible in at least three of four independent re-sizings and 18 that additionally pass device-level checks and supply-temperature corner analysis, compared with 38 and 10 under fixed control. Removing cross-generation memory reduces independently robust discoveries from 54 to 43 and seven-corner robust discoveries from 40 to 27. In DC-DC converter search, nearest-parent analysis identifies a corpus-absent topology whose generated switching current path changes its nearest training-corpus parent from infeasible at all four operating corners to feasible at all four, while increasing median efficiency from 31.2% to 98.96%. These results show that closed-loop generative search can support circuit discovery beyond structural novelty by identifying new topologies with independently verified changes in circuit operation.

eess.SY↗

arXiv2026

Robustness of the \textit{smartpixels} classifier for different simulated sensor geometries and non-ideal detector conditions

Pixel tracking detectors at upcoming collider experiments will see unprecedented charged-particle densities. Real-time data reduction on the detector will enable higher granularity and faster readout, possibly enabling the use of the pixel detector in high-rate online event selection, such as the ATLAS or CMS first-level trigger systems. This data reduction can be accomplished with a neural network (NN) in the readout chip bonded with the sensor that recognizes and rejects tracks with low transverse momentum (p$_T$) based on the geometrical shape of the charge deposition (``cluster''). To design viable detectors for deployment, the dependence of the NN as a function of the sensor geometry, external magnetic field, irradiation, and noise must be understood. In this paper, we present first studies of the efficiency and data reduction for planar pixel sensors exploring these parameters. For the CMS HL-LHC sensor geometry, we obtain a signal efficiency of (91.9 $\pm$ 0.7)% and a data reduction of (29.7 $\pm$ 1.0)%. A smaller sensor pitch in the bending direction improves the p$_T$ discrimination, but a larger pitch can be partially compensated with detector thickness. Any accumulated radiation damage also changes the cluster shape, reducing the signal efficiency compared to the baseline by approximately 30\textendash{}60% in absolute terms, but nearly all of the performance can be recovered through retraining of the network and updating the weights. Finally, the impact of noise was investigated, and retraining the network on noise-injected datasets was found to maintain performance within 6% of the baseline network trained and evaluated on noiseless data.

physics.ins-det↗

arXiv2026

From Generation to Discovery: Diffusion Mutation Kernels for Circuit and Physical Design

Generation and discovery are different problems. A generative model trained on valid artifacts reproduces a distribution, whereas discovery must produce artifacts that lie outside the observed corpus, satisfy hard structural constraints, and improve on established designs under evaluation that the model cannot influence. We introduce a diffusion-based discovery framework. Unlike conventional generative models that sample from learned distributions, it learns transition operators that transform existing artifacts into new candidates. Controlled partial re-noising followed by denoising defines a diffusion mutation kernel, a learned transition distribution that preserves the structural regularities of feasible designs while moving between regions of the design space. The learned model supplies feasibility structure only, and all correctness and performance judgments remain with external engineering tools. Intermediate diffusion trajectories are additionally monitored under a conformal risk budget so that unpromising candidates are discarded before expensive evaluation. We evaluate the framework on three electronic design spaces, an environment that supplies rigorous non-differentiable evaluators in the form of simulation, formal equivalence checking, and industrial physical implementation. The framework discovers 32-bit prefix adders that are formally verified equivalent to addition over all 2^64 input pairs and reduce delay by 17% and area by 18% relative to Kogge-Stone under a placed-and-timed flow; seven independently re-simulated amplifier topologies absent from the training corpus, spanning gains of 21.9-66.1 dB and bandwidths of 72.9 kHz-207 MHz; and macro placements on held-out netlists reaching 0.68x wirelength of an industrial placer.

eess.SY↗

arXiv2026

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

physics.ins-det↗

arXiv2026

On-Detector Machine Learning for Beam-Induced Background Rejection at a 10 TeV Muon Collider

A 10 TeV Muon Collider is a compelling candidate for a future energy-frontier facility, offering unprecedented opportunities to explore the fundamental laws of particle physics. Muon decays in the collider ring produce intense beam-induced background (BIB) that can overwhelm detector occupancy and exceed readout bandwidth constraints. We investigate the potential of on-detector Machine Learning for BIB rejection in the vertex detector, exploiting pixel cluster shapes to distinguish background from collision products. We study three classes of lightweight neural-network architectures, and evaluate their implementation feasibility using high-level synthesis. Selected architectures achieve 88 to 90% data reduction at 99% signal efficiency, while requiring hardware resources compatible with potential ASIC implementation. These results demonstrate the potential of performing substantial BIB rejection directly in the pixel readout, providing a strategy for meeting the tracker readout requirements at a future Muon Collider.

hep-ex↗

arXiv2026

Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors

We present a 28 nm CMOS pixel readout integrated circuit implementing in-pixel analog signal processing and on-chip machine learning data filtering for particle tracking detectors. Our ASIC comprises two $32 \times 8$ pixel matrices with a pixel pitch of $25 \times 25~μ\mathrm{m}^2$, in which each pixel integrates a charge-sensitive amplifier with synchronous auto-zero offset cancellation and a 2-bit flash ADC with programmable thresholds. Two analog front-end architectures, single-ended and differential, are implemented and characterized. Digitized pixel data are combined into row-wise projections and processed by an on-chip, fully combinational neural network classifier for data reduction. Measurements at room temperature using charge injection demonstrate an equivalent noise charge of $54.6~\mathrm{e}^{-}$ and a threshold dispersion of $\sim$78.2~\unit{\electron} at nominal bias, linear response up to several~\unit{\kilo\electron}, and stable operation at a 10~MHz clock frequency. The neural network output is compared with offline RTL predictions and agrees for $99.06\%$ of $1.5 \times 10^{5}$ test inputs.

physics.ins-det↗

arXiv2026

Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging

Large language models (LLMs) have enabled natural-language-driven automation of electronic design automation (EDA) workflows, but reliable execution of generated scripts remains a fundamental challenge. In LLM-based EDA tasks, failures arise not from syntax errors but from violations of implicit structural dependencies over design objects, including invalid acquisition paths, missing prerequisites, and incompatible API usage. Existing approaches address these failures through tool-in-the-loop debugging, repeatedly executing and repairing programs using runtime feedback. While effective, this paradigm couples correctness to repeated tool invocation, leading to high latency and poor scalability in multi-step settings. We propose to eliminate tool-in-the-loop debugging by enforcing structural correctness prior to execution. Each task is represented as a structural dependency graph that serves as an explicit execution contract, and a verifier-guided synthesis framework enforces this contract through graph-conditioned retrieval, constrained generation, and staged pre-execution verification with diagnosis-driven repair. On single-step tasks, our method improves pass rate from 73.0% (LLM+RAG) and 76.0% (tool-in-loop) to 82.5%, while requiring exactly one tool call per task and reducing total tool calls by more than 2x. On multi-step tasks, pass rate improves from 30.0% to 70.0%, and further to 84.0% with trajectory-level reflection. Uncertainty-aware filtering further reduces verifier false positives from 20.0% to 6.7% and improves precision from 80.0% to 93.3%. These results show that enforcing structural consistency prior to execution decouples correctness from tool interaction, improving both reliability and efficiency in long-horizon EDA code generation.

cs.SE↗