arXiv subjects

Aravind Saravanan

Publications and source records attributed to Aravind Saravanan.

3 recordsLinked to original sources

arXiv2026

Delta-Seeker: Closed-Loop Generative Search for Novel Circuit Design Discovery

Generative models are increasingly used for circuit synthesis and optimization by proposing topologies, sizing devices, and exploring large design spaces. We investigate whether they can instead support design discovery, where generated structures must depart from known designs while producing reproducible electrical behavior. We propose Delta-Seeker, a closed-loop circuit search framework that combines discrete diffusion for topology generation and mutation with structural checking, SPICE-in-the-loop sizing, Pareto selection, and feedback from prior search outcomes. The search controller uses progress and recurring structural failures to allocate evaluation effort and steer subsequent topology generation, while independent re-sizing and operating-corner analysis are performed only after search. In generator-only experiments, cross-generation feedback increases structurally valid children from 143 to 945 and reduces the faulty-candidate fraction from 0.925 to 0.761. In op-amp topology discovery at matched sizing cost, Delta-Seeker yields 54 designs that remain feasible in at least three of four independent re-sizings and 18 that additionally pass device-level checks and supply-temperature corner analysis, compared with 38 and 10 under fixed control. Removing cross-generation memory reduces independently robust discoveries from 54 to 43 and seven-corner robust discoveries from 40 to 27. In DC-DC converter search, nearest-parent analysis identifies a corpus-absent topology whose generated switching current path changes its nearest training-corpus parent from infeasible at all four operating corners to feasible at all four, while increasing median efficiency from 31.2% to 98.96%. These results show that closed-loop generative search can support circuit discovery beyond structural novelty by identifying new topologies with independently verified changes in circuit operation.

eess.SY↗

arXiv2026

From Generation to Discovery: Diffusion Mutation Kernels for Circuit and Physical Design

Generation and discovery are different problems. A generative model trained on valid artifacts reproduces a distribution, whereas discovery must produce artifacts that lie outside the observed corpus, satisfy hard structural constraints, and improve on established designs under evaluation that the model cannot influence. We introduce a diffusion-based discovery framework. Unlike conventional generative models that sample from learned distributions, it learns transition operators that transform existing artifacts into new candidates. Controlled partial re-noising followed by denoising defines a diffusion mutation kernel, a learned transition distribution that preserves the structural regularities of feasible designs while moving between regions of the design space. The learned model supplies feasibility structure only, and all correctness and performance judgments remain with external engineering tools. Intermediate diffusion trajectories are additionally monitored under a conformal risk budget so that unpromising candidates are discarded before expensive evaluation. We evaluate the framework on three electronic design spaces, an environment that supplies rigorous non-differentiable evaluators in the form of simulation, formal equivalence checking, and industrial physical implementation. The framework discovers 32-bit prefix adders that are formally verified equivalent to addition over all 2^64 input pairs and reduce delay by 17% and area by 18% relative to Kogge-Stone under a placed-and-timed flow; seven independently re-simulated amplifier topologies absent from the training corpus, spanning gains of 21.9-66.1 dB and bandwidths of 72.9 kHz-207 MHz; and macro placements on held-out netlists reaching 0.68x wirelength of an industrial placer.

eess.SY↗

arXiv2026

Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging

Large language models (LLMs) have enabled natural-language-driven automation of electronic design automation (EDA) workflows, but reliable execution of generated scripts remains a fundamental challenge. In LLM-based EDA tasks, failures arise not from syntax errors but from violations of implicit structural dependencies over design objects, including invalid acquisition paths, missing prerequisites, and incompatible API usage. Existing approaches address these failures through tool-in-the-loop debugging, repeatedly executing and repairing programs using runtime feedback. While effective, this paradigm couples correctness to repeated tool invocation, leading to high latency and poor scalability in multi-step settings. We propose to eliminate tool-in-the-loop debugging by enforcing structural correctness prior to execution. Each task is represented as a structural dependency graph that serves as an explicit execution contract, and a verifier-guided synthesis framework enforces this contract through graph-conditioned retrieval, constrained generation, and staged pre-execution verification with diagnosis-driven repair. On single-step tasks, our method improves pass rate from 73.0% (LLM+RAG) and 76.0% (tool-in-loop) to 82.5%, while requiring exactly one tool call per task and reducing total tool calls by more than 2x. On multi-step tasks, pass rate improves from 30.0% to 70.0%, and further to 84.0% with trajectory-level reflection. Uncertainty-aware filtering further reduces verifier false positives from 20.0% to 6.7% and improves precision from 80.0% to 93.3%. These results show that enforcing structural consistency prior to execution decouples correctness from tool interaction, improving both reliability and efficiency in long-horizon EDA code generation.

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