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Hoseok Kim

Publications and source records attributed to Hoseok Kim.

2 recordsLinked to original sources

BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference

Modern edge System-on-Chips (SoCs) integrate increasingly heterogeneous processing units (PUs) such as CPUs, GPUs, and NPUs, yet current inference stacks still map entire models to a single PU, leaving significant performance and energy efficiency on the table. This limitation is exacerbated by emerging neural architectures such as state-space models (SSMs), Kolmogorov-Arnold networks (KANs), and multi-stage vision-language-action (VLA) pipelines, whose diverse operator characteristics are not uniformly suited to any single PU. We present BIDENT, a unified operator-level orchestration framework for heterogeneous edge inference that maps individual operators to the most suitable PU based on profiled execution characteristics. BIDENT formulates operator-to-PU assignment as a shortest-path problem over a weighted execution graph, enabling efficient and principled scheduling under the profiled cost model for both latency and energy minimization objectives. Unlike prior work that relies on model-specific heuristics or coarse-grained partitioning, BIDENT provides a model-agnostic framework that jointly supports sequential execution, intra-model parallelism across independent operators, and concurrent co-scheduling of two inference requests within a single formulation. Evaluated on an Intel Core Ultra SoC across ten model families and 190 concurrent model pairs, BIDENT achieves up to 1.60x single-model speedup, reduces energy by 9.2% on average, and delivers a 2.28x geometric-mean concurrent speedup over a naive multi-PU placement baseline.

cs.AR↗

TESSERA: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs

AI model architectures are diversifying rapidly. While CNNs and transformers rely on dense matrix multiplication, emerging architectures (state-space models, fast Fourier transform (FFT)-based long convolutions, Kolmogorov-Arnold networks, and spiking networks) are not multiply-accumulate (MAC) dominated; they spend much of their computation on vector and non-MAC primitives that homogeneous, MAC-centric neural processing units (NPUs) serve poorly. This motivates heterogeneous NPUs (HPUs) built from non-identical tiles. However, prior designs vary only one or two architectural dimensions and target narrow workloads, while existing frameworks lack support for jointly exploring fine-grained tile-level heterogeneity. We present TESSERA, an analytical simulator and design-space-exploration (DSE) framework for HPU microarchitecture design. TESSERA jointly explores tile-type composition (large Big, small Little, and non-MAC Special-Function tiles), MAC array size, precision, dataflow, sparsity mode, MAC engine type, and special-function units for FFT, spiking-integrate, and polynomial operators. Unlike prior simulators that assume a single homogeneous tile type, TESSERA provides dedicated energy, area, and timing models for non-MAC tiles and maps operators across heterogeneous tiles with a heterogeneity-aware compiler. A multi-seed DSE pipeline combines stratified sampling with genetic-algorithm refinement to identify Pareto-optimal designs. Cost models are calibrated to a 7 nm node and cross-validated against NVIDIA's Deep Learning Accelerator (NVDLA). Across a 20-workload suite, the best general-purpose HPU found by TESSERA (~200 mm^2, Big+Little+Special-Function) achieves 46.91% mean energy savings over the best iso-area homogeneous baseline.

cs.AR↗