Katsuhiro Seta

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.