Restoring Sparsity in Potts Machines via Mean-Field Constraints
Ising machines and related probabilistic hardware have emerged as promising platforms for NP-hard optimization and sampling. However, many practical problems involve constraints that induce dense or all-to-all couplings, undermining scalability and hardware efficiency. We address this constraint-induced density through two complementary approaches. First, we introduce a hardware-aware native formulation for multi-state probabilistic digits (p-dits) that avoids the locally dense intra-variable couplings required by binary Ising encodings. We validate p-dit dynamics by reproducing known critical behavior of the 2D Potts model. Second, we propose mean-field constraints (MFC), a hybrid scheme that replaces dense pairwise constraint couplings with dynamically updated single-node biases. Applied to balanced graph partitioning, MFC achieves solution quality comparable to exact all-to-all constraint formulations while dramatically reducing graph density. Finally, we demonstrate the practical impact of restored sparsity through an FPGA implementation. In comparisons using FPGA kernel time and CPU solver-loop time, and excluding the current prototype's host-device schedule transfer overhead, the FPGA reaches the 50% success threshold more than an order of magnitude faster than the CPU probabilistic solvers and more than two orders of magnitude faster than the Tabu Ising baseline. Together, these results outline a pathway for scaling constrained optimization on probabilistic hardware.