arXiv subjects

Luca Larcher

Publications and source records attributed to Luca Larcher.

2 recordsLinked to original sources

arXiv2026

Experiments and Modeling of Defect Dynamics and BTI Behavior in Doped InO TFTs during $400^\circ$C Post-Processing Forming Gas Annealing

We investigate the impact of a monolithic three-dimensional (M3D) integration process-critical $400^\circ$C post-processing forming gas anneal (FGA) on the electrical performance, reliability, and defect evolution of oxide-channel thin-film transistors (TFTs), combining systematic experiments with density-functional-theory (DFT)-based liquid-quench molecular-dynamics (MD) simulations. Indium tungsten oxide (IWO) TFTs are employed as a model system and encapsulated with a thin 3 nm Al$_2$O$_3$ / 3 nm HfO$_2$ hybrid layer that effectively suppresses external hydrogen ingress. We reveal a non-monotonic evolution of device behavior during FGA, governed by initial densification followed by partial crystallization. Short-duration FGA (10 min) induces channel densification and the formation of shallow, delocalized defect states, leading to pronounced positive bias temperature instability (PBTI) degradation and the emergence of a characteristic transfer-curve "kink." With prolonged annealing (>40 min), partial crystallization of the oxide channel occurs, stabilizing hydrogen in deep, localized defect states, suppressing hydrogen mobility, and restoring device reliability. As a result, the PBTI shift is reduced to 10.4 mV after 2000 seconds of stress, accompanied by complete elimination of the transfer-curve kink. These findings provide a mechanistic understanding of hydrogen-defect interactions during high-temperature post-processing FGA and demonstrate that appropriate hydrogen-blocking encapsulation enables oxide-channel TFT integration without compromising electrical performance or reliability.

cond-mat.mtrl-sci↗

arXiv2026

System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability

Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce larger cell-level parasitic resistance and capacitance (RC). In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in A7 CFET and A10 NSFET technology nodes. Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation. Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow. The results of the AI accelerator design demonstrate that the A7 CFET reduces the chip area by 24.7% and the total wire length by 12%, improving the area efficiency TOPS/mm^2 by 74% relative to the baseline of the A10 NSFET. Under iso-frequency operation, results reveal that CFET voltage scaling reduces power by 68% and lowers power density from 148 W/cm^2 to 55 W/cm^2, which reduces the chip's temperature from 125 degrees C down to merely 62 degrees C. The resulting reduction in stress temperature suppresses 10-year BTI-induced degradation by 39%, reducing the required aging timing guardband by 53%.

cs.ET↗