arXiv subjects

Maximilian Kirschner

Publications and source records attributed to Maximilian Kirschner.

3 recordsLinked to original sources

arXiv2026

Automated Deployment of Real-Time Tasks for Phased Execution on Scratchpad-Based Multicore Platforms

The increasing throughput demands in real-time systems and the consolidation of functionality on few, high-performance platforms are driving a shift towards parallel architectures. A key challenge for multicore real-time systems is the interference from contention for access to shared memory. Phased execution approaches address this challenge by restricting shared memory access to mutually exclusive memory phases, while computation is limited to memories local to each core. However, the complexity of managing and scheduling said memory phases hinders the adoption of phased execution in real-time applications. To address this challenge, we propose a model-based deployment methodology that automates the process of adapting applications to phased execution. We present an integrated tool-based deployment process that extends the application through the necessary memory phases and provides a runtime environment to orchestrate execution on the target hardware platform. Our approach requires minimal changes to the application implementation since the deployment tool directly extracts the required information from the generated application binaries. We validate our methodology using an avionics case study on a RISC-V multicore system, showcasing its key components and principles of operation.

cs.SE↗

arXiv2025

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. We present a new hardware architecture to bridge this gap between performance and predictability. The architecture features a multi-core vector processor with predictable cores, each equipped with local scratchpad memories. A central management core orchestrates access to shared external memory following a statically determined schedule. To evaluate the proposed hardware architecture, we analyze different variants of our parameterized design. We compare these variants to a baseline architecture consisting of a single-core vector processor with large vector registers. We find that configurations with a larger number of smaller cores achieve better performance due to increased effective memory bandwidth and higher clock frequencies. Crucially for real-time systems, execution time fluctuation remains very low, demonstrating the platform's time predictability.

cs.AR↗

arXiv2024

Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor

Neural networks are increasingly used in real-time systems, such as automated driving applications. This requires high-performance hardware with predictable timing behavior. State-of-the-art real-time hardware is limited in memory and compute resources. On the other hand, modern accelerator systems lack the necessary predictability properties, mainly due to interference in the memory subsystem. We present a new hardware architecture with an accompanying compiler-based deployment toolchain to close this gap between performance and predictability. The hardware architecture consists of a multicore vector processor with predictable cores, each with local scratchpad memories. A central management core facilitates access to shared external memory through a static schedule calculated at compile-time. The presented compiler exploits the fixed data flow of neural networks and WCET estimates of subtasks running on individual cores to compute this schedule. Through this approach, the WCET estimate of the overall system can be obtained from the subtask WCET estimates, data transfer times, and access times of the shared memory in conjunction with the schedule calculated by the compiler.

cs.AR↗