Photonic sequential logic circuits for stateful intelligence
By virtue of its high energy efficiency and ultra-low latency, optical computing is regarded as a highly promising computing paradigm in the post-Moore era. However, constructing a Turing-complete optical computing for next-generation AI paradigms, from large language models (LLMs) to real-time autonomous systems, requires not only stateless function mapping units, but also sequential logic circuits capable of storing historical states and processing dynamic data streams. Current photonic processors lack this temporal memory, and the state-of-the-art optical sequential schemes remain impractical due to signal attenuation and the absence of programmable clock control. Here, we propose a photonic sequential logic circuits (PSLC) to resolve this fundamental challenge. Leveraging a uniquely designed active optoelectronic feedback network, we construct a complete family of photonic sequential logic devices, comprehensively encompassing set-reset latches, D latches, and edge-triggered master-slave D flip-flops. We further construct photonic sequence detectors and asynchronous counters, verifying the capability of the architecture to execute both synchronous and asynchronous sequential tasks, alongside its system-level scalability. Ultimately, by combining the constructed PSLC with stateless function mapping units, we establish a universal hardware paradigm for stateful intelligence. We validate this paradigm by executing highly reliable real-time drone obstacle avoidance in the physical domain, alongside Shakespearean-style text generation in the symbolic domain. This work provides the crucial missing piece of the puzzle for optical computing to achieve stateful computing, establishing a definitive hardware foundation for advancing toward Turing-complete optical computing.