arXiv subjects

Qifan Zhang

Publications and source records attributed to Qifan Zhang.

39 records · Page 3Linked to original sources

arXiv2021

Learning Nash Equilibria in Zero-Sum Stochastic Games via Entropy-Regularized Policy Approximation

We explore the use of policy approximations to reduce the computational cost of learning Nash equilibria in zero-sum stochastic games. We propose a new Q-learning type algorithm that uses a sequence of entropy-regularized soft policies to approximate the Nash policy during the Q-function updates. We prove that under certain conditions, by updating the regularized Q-function, the algorithm converges to a Nash equilibrium. We also demonstrate the proposed algorithm's ability to transfer previous training experiences, enabling the agents to adapt quickly to new environments. We provide a dynamic hyper-parameter scheduling scheme to further expedite convergence. Empirical results applied to a number of stochastic games verify that the proposed algorithm converges to the Nash equilibrium, while exhibiting a major speed-up over existing algorithms.

cs.LG↗

arXiv2020

Toward Terabits-per-second Communications: A High-Throughput Hardware Implementation of $G_N$-Coset Codes

Recently, a parallel decoding algorithm of $G_N$-coset codes was proposed.The algorithm exploits two equivalent decoding graphs.For each graph, the inner code part, which consists of independent component codes, is decoded in parallel. The extrinsic information of the code bits is obtained and iteratively exchanged between the graphs until convergence. This algorithm enjoys a higher decoding parallelism than the previous successive cancellation algorithms, due to the avoidance of serial outer code processing. In this work, we present a hardware implementation of the parallel decoding algorithm, it can support maximum $N=16384$. We complete the decoder's physical layout in TSMC $16nm$ process and the size is $999.936μm\times 999.936μm, \,\approx 1.00mm^2$. The decoder's area efficiency and power consumption are evaluated for the cases of $N=16384,K=13225$ and $N=16384, K=14161$. Scaled to $7nm$ process, the decoder's throughput is higher than $477Gbps/mm^2$ and $533Gbps/mm^2$ with five iterations.

cs.IT↗

arXiv2018

A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET

Polar codes has been selected as 5G standard. However, only a couple of ASIC featuring decoders are fabricated,and none of them support list size L > 4 and code length N > 1024. This paper presents an ASIC implementation of three decoders for polar code: successive cancellation (SC) decoder, flexible decoder and ultra-reliable decoder. These decoders are all SC based decoder, supporting list size up to 1,8,32 and code length up to 2^15,2^14,2^11 respectively. This chip is fabricated in a 16nm TSMC FinFET technology, and can be clocked at 1 Ghz. Optimization techniques are proposed and employed to increase throughput. Experiment result shows that the throughput can achieve up to 5.16Gbps. Compared with fabricated AISC decoder and synthesized decoder in literature, the flexible decoder achieves higher area efficiency.

cs.IT↗