TESSERA: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
AI model architectures are diversifying rapidly. While CNNs and transformers rely on dense matrix multiplication, emerging architectures (state-space models, fast Fourier transform (FFT)-based long convolutions, Kolmogorov-Arnold networks, and spiking networks) are not multiply-accumulate (MAC) dominated; they spend much of their computation on vector and non-MAC primitives that homogeneous, MAC-centric neural processing units (NPUs) serve poorly. This motivates heterogeneous NPUs (HPUs) built from non-identical tiles. However, prior designs vary only one or two architectural dimensions and target narrow workloads, while existing frameworks lack support for jointly exploring fine-grained tile-level heterogeneity. We present TESSERA, an analytical simulator and design-space-exploration (DSE) framework for HPU microarchitecture design. TESSERA jointly explores tile-type composition (large Big, small Little, and non-MAC Special-Function tiles), MAC array size, precision, dataflow, sparsity mode, MAC engine type, and special-function units for FFT, spiking-integrate, and polynomial operators. Unlike prior simulators that assume a single homogeneous tile type, TESSERA provides dedicated energy, area, and timing models for non-MAC tiles and maps operators across heterogeneous tiles with a heterogeneity-aware compiler. A multi-seed DSE pipeline combines stratified sampling with genetic-algorithm refinement to identify Pareto-optimal designs. Cost models are calibrated to a 7 nm node and cross-validated against NVIDIA's Deep Learning Accelerator (NVDLA). Across a 20-workload suite, the best general-purpose HPU found by TESSERA (~200 mm^2, Big+Little+Special-Function) achieves 46.91% mean energy savings over the best iso-area homogeneous baseline.