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Zhen Wu

Publications and source records attributed to Zhen Wu.

2 recordsLinked to original sources

Neutralizing Popularity Bias in LLM-based Recommendation via Counterfactual Reasoning Guidelines

In the era of generative AI, recommender systems are moving from precise prediction to trustworthy generation. Large language models (LLMs) support this shift by inferring user interests and producing natural-language explanations. However, LLM-based recommendation suffers from a fundamental obstacle: popularity bias. Through pre-training on massive corpora, LLMs tend to rely on global statistics and trend signals, yielding recommendations that follow popularity rather than genuine preference. As this bias is entangled in model parameters and is hard to remove directly, we propose Neutralizing Popularity Bias in LLM-based Recommendation via Counterfactual Reasoning Guidelines (NPRec), a model-agnostic framework that mitigates popularity bias through external semantic intervention. NPRec performs counterfactual refinement to causally separate intrinsic user interests from popularity-driven conformity, producing debiased textual guidelines that reflect actual user preferences. These guidelines are injected at inference time to shift the LLM from unconstrained generation to guided reasoning, without any parameter updates. Serving as explicit premises, they both ground faithful explanations and improve recommendation quality. Extensive experiments on three real-world datasets demonstrate that NPRec achieves promising performance in recommendation accuracy, explanation quality, and debiasing capability.

cs.AI

CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration

Large language model (LLM) inference exhibits substantial variability across adaptation modes, context lengths, and request concurrency, creating challenges for maintaining high utilization, memory efficiency, and scalable performance on compute-in-memory (CIM) accelerators. This paper presents CHIPSMORE, a multi-mode and multi-request LLM inference accelerator that integrates compute-in-interconnect and CIM to support both base-mode and low-rank adaptation (LoRA) inference under diverse workloads. CHIPSMORE employs heterogeneous processing elements consisting of resistive RAM analog compute-in-memory (RRAM-ACIM) and static RAM digital compute-in-memory (SRAM-DCIM) interconnected through a programmable Inter-PE computational network (IPCN). A composable hierarchical key-value (KV) memory scheme dynamically allocates router scratchpad, SRAM-DCIM, and embedded DRAM (eDRAM) resources according to workload requirements, enabling scalable support for long-context and batched inference. Furthermore, a non-replicated multi-request execution pipeline exploits request-level parallelism without duplicating pretrained weights, while a state-aware resource reconfiguration mechanism selectively retains runtime states and power-gates inactive resources to improve energy efficiency. Evaluation using cycle-accurate hardware-software co-simulation demonstrates that CHIPSMORE effectively sustains high throughput across varying model sizes, context lengths, and batch sizes while maintaining favorable power scaling. Compared with Nvidia H100, CHIPSMORE achieves up to $2.38\times$ higher throughput and $27\times$ higher energy efficiency on Mistral-7B inference while eliminating weight replication for multi-request serving.

cs.AR