Piezoresistance in Silicon and its nanostructures

Abstract

Piezoresistance is the change in the electrical resistance, or more specifically the resistivity, of a solid induced by an applied mechanical stress. The origin of this effect in bulk, crystalline materials like Silicon, is principally a change in the electronic structure which leads to a modification of the charge carriers effective mass. The last few years have seen a rising interest in the piezoresistive properties of semiconductor nanostructures, motivated in large part by claims of a giant piezoresistance effect in Silicon nanowires that is more than two orders of magnitude bigger than the known bulk effect. This review aims to present the controversy surrounding claims and counter-claims of giant piezoresistance in Silicon nanostructures by presenting a summary of the major works carried out over the last 10 years. The main conclusions that can be drawn from the literature are that i) reproducible evidence for a giant piezoresistance effect in un-gated Silicon nanowires is limited, ii) in gated nanowires a giant effect has been reproduced by several authors, iii) the giant effect is fundamentally different from either the bulk Silicon piezoresistance or that due to quantum confinement in accumulation layers and heterostructures, the evidence pointing to an electrostatic origin for the piezoresistance, iv) released nanowires tend to have slightly larger piezoresistance coefficients than un-released nanowires, and v) insufficient work has been performed on bottom-up grown nanowires to be able to rule out a fundamental difference in their properties when compared with top-down nanowires. On the basis of this, future possible research directions are suggested.