Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities

Jiaying Zhu; Ziyang Zheng; Zhengyuan Shi; Yalun Cai; Qiang Xu

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arXiv · 2508.04235

Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities

Jiaying Zhu·Ziyang Zheng·Zhengyuan Shi·Yalun Cai·Qiang Xu

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Abstract

Circuit Satisfiability (CSAT) plays a pivotal role in Electronic Design Automation. The standard workflow for solving CSAT problems converts circuits into Conjunctive Normal Form (CNF) and employs generic SAT solvers powered by Conflict-Driven Clause Learning (CDCL). However, this process inherently discards rich structural and functional information, leading to suboptimal solver performance. To address this limitation, we introduce CASCAD, a novel circuit-aware SAT solving framework that directly leverages circuit-level conditional probabilities computed via Graph Neural Networks (GNNs). By explicitly modeling gate-level conditional probabilities, CASCAD dynamically guides two critical CDCL heuristics -- variable phase selection and clause managementto significantly enhance solver efficiency. Extensive evaluations on challenging real-world Logical Equivalence Checking (LEC) benchmarks demonstrate that CASCAD reduces solving times by up to 10x compared to state-of-the-art CNF-based approaches, achieving an additional 23.5% runtime reduction via our probability-guided clause filtering strategy. Our results underscore the importance of preserving circuit-level structural insights within SAT solvers, providing a robust foundation for future improvements in SAT-solving efficiency and EDA tool design.

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Jiaying Zhu, Ziyang Zheng, Zhengyuan Shi, Yalun Cai, Qiang Xu. 2025-08-06. Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities. https://arxiv.org/abs/2508.04235

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