Digital Etching of Single-Crystalline Silicon Fin Barriers Down to Sub-10 nm

Abstract

This work presents a fabrication process to realize sub-10 nm-thick, high-aspect-ratio Si fins using high-resistivity float-zone single-crystal Si wafers. Following anisotropic wet etching, a digital etching process based on repeated rapid thermal annealing (RTA) oxidation and vapor-phase hydrofluoric acid (VHF) etching of the resulting oxide was developed, enabling thinning of Si fins into the sub-10 nm regime. Cross-sectional scanning transmission electron microscopy confirms fin thicknesses as thin as 6 nm, although with a tapered profile resulting from the initial anisotropic wet etch. Tapering of the fin was reduced by using an N{_2}/O{_2} (5:1) ambient together with a reduced ramp rate during the temperature ramping for the RTA oxidation process. A thickness variation of 3 nm along a 1.2 μm tall fin was achieved on a fin with 12 nm near the top and 15 nm near the base. The developed process provides a pathway for fabricating Josephson junctions, setting a foundation toward reproducible and scalable superconducting qubit fabrication with single-crystal Si dielectric barriers using readily available Si processing technology.