Simulations of MAPS designs for FCC-ee

Abstract

Future electron-positron colliders such as the future circular collider require vertex detectors with excellent spatial resolution and a low material budget. Monolithic active pixel sensors (MAPS) are a leading candidate technology because they integrate the sensing volume and readout electronics within a single thin silicon substrate and can operate at power densities compatible with air cooling. This paper presents the design and optimization of a high-voltage MAPS (HV-MAPS) pixel structure with a thickness of 25 $μ\text{m}$ and a pitch of 50 $μ\text{m}$, developed using TCAD process and device simulations. The implantation energies and doses of the top-side implants are optimized with respect to the maximum electric field, sensor capacitance, and signals induced at each contact by minimum-ionizing particles. The optimized design reaches full depletion at a bias voltage of approximately -3 V and has an estimated breakdown voltage magnitude of 300-390 V. At a bias voltage of -100 V, the simulated charge-collection efficiency is approximately 90% outside the well regions and 80% within them and remains nearly independent of the angle of incidence.