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arXiv · 2610.39570

LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation

Leo Itoh·Junichiro Kadomoto
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Abstract

Long-run RTL simulation of CPU candidates can take hours, while short diagnostic runs may miss performance degradation that emerges later in execution. This evaluation cost can delay design decisions in LLM-agent-based CPU development. We present a development environment in which LLM agents implement CPU candidates on an FPGA and use on-board performance measurements to guide design decisions. We applied it to the human-supervised development of a single-cycle RV32I core into a three-wide out-of-order RV32IM core. The final design reaches 5.61 CoreMark/MHz at 130 MHz on a Artix-7 FPGA. For the same CPU candidate running 8,000 CoreMark iterations, FPGA evaluation, including implementation, was 9.6x faster than single-threaded RTL simulation. In one case, board measurements revealed long-run performance degradation in a candidate that improved in a short diagnostic run. The result guided candidate selection and led to RTL-based root-cause analysis and a fix.

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Leo Itoh, Junichiro Kadomoto. 2026-10-29. LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation. https://arxiv.org/abs/2610.39570

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