Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics

Abstract

Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. As equivalent oxide thickness is reduced, however, finite interfacial responses can increasingly constrain gate control [1-5]. Here we show that this screening boundary can itself be engineered by converting the surface of the topological insulator Bi2Se3 into insulating high-kappa$ BiF3. Position-resolved calculations reveal a gap-opened immediate amorphous-BiF3/crystalline-Bi2Se3 interface and a reconstructed gap-closed Bi2Se3-derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Independently, capacitor measurements resolve a finite series response consistent with the electronic compressibility of this buried boundary, which reduces rather than enhances the nominal stack capacitance. Despite this capacitance penalty, MoS2 transistors with closely matched BiF3 thicknesses and a common BiF3/MoS2 channel-side material interface exhibit near-thermionic switching, negligible hysteresis, and approximately sevenfold lower drain-induced barrier lowering than BiF3-only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.